Foundries & Manufacturing The Four Pillars of Semiconductors - Lesson 3

Learning Path: 🔧 Toolmakers → 🏛️ Architects → 🏭 Foundries → ⚙️ Workhorses

Level: Beginner-friendly | Estimated reading time: 25–30 minutes Introduction

You've learned what semiconductors are and why they matter. You've seen how chip designers create the blueprints. Now comes the central question that shapes everything else in this industry: who actually builds the chip?

The answer is a foundry - and understanding how foundries work, where they sit in the global economy, and why so few of them exist at the leading edge is one of the most important things you can learn about the modern world.

This lesson takes you from raw silicon wafers all the way through to a finished chip, then zooms out to show you the economic and geopolitical forces that surround every step of that process.

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What Is a Foundry?

A foundry - also called a fab, short for fabrication plant - is a company that manufactures semiconductor chips on behalf of chip designers. Foundries do not design chips of their own. They receive a completed design file from an Architect (a company like NVIDIA, Apple, or Qualcomm) and use their factories to physically produce that design at massive scale.

A simple way to think about it: an Architect is like an author who writes a detailed blueprint. A foundry is like the printing press that turns that blueprint into millions of physical copies.

Most major foundries operate on a pure-play model - they manufacture exclusively for others and do not sell chips under their own brand. This neutrality is a deliberate business strategy. It allows foundries to serve competing chip companies simultaneously, because clients know the foundry has no stake in the chip market itself. TSMC, for example, manufactures chips for Apple, NVIDIA, AMD, and Qualcomm - companies that compete fiercely in the marketplace - all under one roof.

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How Foundries Connect to the Other Pillars

Foundries sit at the center of the semiconductor supply chain, depending on both Toolmakers and Architects to function:

- Toolmakers supply foundries with the machines, chemicals, and materials needed to operate - lithography equipment, etching tools, specialty gases, and silicon wafers. Without Toolmakers, the fab cannot run.

- Architects supply foundries with chip design files that specify exactly what must be built. Without Architects, the foundry has nothing to produce.

- Workhorses - including packaging and testing specialists - receive the finished dies that foundries produce and transform them into deployable products.

Remove any one of these relationships and the chain breaks. The foundry is where those relationships converge into something physical.

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Silicon Wafers - Where Every Chip Begins

Before a foundry can manufacture a chip, it needs a silicon wafer - a thin, circular disk of ultra-pure silicon that serves as the base on which all chip structures are built.

A single wafer, typically 300mm (about 12 inches) in diameter, can hold hundreds of individual chips simultaneously. Producing a wafer involves several steps:

Mining and refining - Raw quartz sand is processed and refined until it reaches extreme purity - sometimes described as 99.9999999% pure silicon, which the industry calls "nine-nines pure." Even trace amounts of contamination can disrupt the electrical behavior of chips built on top.

Crystal growth - The purified silicon is melted and a small seed crystal is slowly pulled upward and rotated through the melt. This process forms a large cylindrical ingot with a perfectly uniform crystal structure throughout.

Slicing - The ingot is cut into thin wafers using a diamond-tipped wire saw, each just a fraction of a millimeter thick.

Polishing - Wafers are polished to an atomic-level smoothness. Microscopic surface irregularities - invisible to the naked eye - can disrupt manufacturing precision and reduce the percentage of working chips on the finished wafer.

The quality of the starting wafer directly determines yield - the percentage of chips on the wafer that turn out functional. This is why silicon wafer production is its own specialized discipline, dominated by a small number of companies with decades of crystal growth expertise.

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Lithography - Printing Circuits with Light

Chip circuits are almost incomprehensibly small. Modern chips contain transistors measured in just a few nanometers - for scale, a human hair is roughly 80,000 nanometers wide. No physical cutting tool can work at this scale. Instead, foundries use light to print circuit patterns onto the wafer in a process called lithography.

How Lithography Works

Step 1 - Apply photoresist. A light-sensitive chemical called photoresist is coated onto the wafer's surface in a thin, uniform layer.

Step 2 - Expose with light. A lithography machine shines light through a photomask - a glass plate etched with the circuit pattern for one layer of the chip. The light passes through the mask and projects the pattern onto the photoresist below.

Step 3 - Develop. Where light strikes the photoresist, a chemical change occurs. When developed, the exposed or unexposed areas dissolve away - similar to developing a photograph - leaving behind the circuit pattern.

Step 4 - Etch. The exposed areas of the underlying material are etched away - carved out chemically - to define the physical structures of the chip.

Step 5 - Strip and clean. Remaining photoresist is removed and the wafer is cleaned. One layer is complete.

This entire cycle repeats dozens to over one hundred times - once for each layer of the chip's structure.

EUV Lithography

Standard lithography uses deep ultraviolet (DUV) light, capable of defining features down to approximately 7 nanometers. To go smaller - to 5nm, 3nm, or 2nm - foundries use Extreme Ultraviolet (EUV) lithography.

EUV light has a wavelength of just 13.5 nanometers. It is absorbed by almost every material, including air, so EUV machines must operate in a near-perfect vacuum and use mirrors instead of lenses. Generating EUV light requires firing a laser at tiny droplets of tin at 50,000 times per second.

Only one company in the world manufactures EUV lithography machines: ASML of the Netherlands. A single machine costs approximately $380 million. There is no substitute, and every leading-edge foundry in the world depends on them.

--- Front-End Fabrication (FEOL)

Front-end fabrication - known in the industry as the Front End of Line (FEOL) - refers to all the manufacturing steps that create the active components of the chip directly in and on the silicon wafer. This is where the transistors are formed, and it is the most technically demanding phase of chip manufacturing.

### The Key FEOL Steps

Wafer preparation and cleaning - The polished wafer is cleaned using ultra-pure water and chemicals to remove any organic or metallic contaminants. Even a single atom of the wrong material in the wrong place can damage a transistor.

Deposition - Ultra-thin layers of material are applied to the wafer surface using techniques like Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). These layers may be insulators, conductors, or semiconductors, and must be precisely controlled in both composition and thickness - sometimes down to a single atom.

Lithography - As described above, each layer's circuit pattern is projected and developed onto the wafer. This step is performed separately for each distinct layer of the chip.

Etching - Material is removed from exposed areas using plasma or wet chemical etching, carving circuit features into the deposited layers with sub-nanometer precision.

Ion implantation - Charged particles called ions are fired into specific regions of the silicon at controlled energies. This doping process deliberately introduces impurities that alter the electrical properties of those regions - defining which areas of the transistor will conduct current and which will block it.

Annealing - After ion implantation, the wafer is heated in a controlled environment. This activates the implanted ions and repairs any crystal damage caused by the implantation process.

Wafer-level testing - At key stages, the foundry tests the wafer electrically to verify that structures built so far are performing correctly. Catching problems early reduces waste and allows the process to be adjusted before more layers are added.

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## Back-End Fabrication (BEOL)

Once transistors are formed, the chip enters the Back End of Line (BEOL) phase. This is where the metal wiring layers are added to connect transistors to each other and to the chip's external contacts.

A modern chip may have ten or more metal wiring layers stacked above the transistors. The lower layers carry short-range connections between nearby transistors. The upper layers carry power and global signals across longer distances.

Each metal layer is separated from the next by an interlayer dielectric - an insulating material that prevents the layers from short-circuiting. The metal of choice for most modern BEOL processes is copper, which offers lower electrical resistance than earlier aluminum-based wiring.

At the very top of the stack, a passivation layer protects the chip from moisture and contamination, and bond pads - exposed metal areas - provide the connection points that will later be wired or bumped to the chip's package.

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## Technical Layers of a Finished Chip

A completed chip is a three-dimensional stack of precisely engineered layers, each performing a specific function. Here is what those layers are, from bottom to top:

The substrate - The silicon wafer itself, or the portion of it where transistors are formed. All active electrical behavior originates here.

The transistor layer - Built directly in and on the silicon substrate during FEOL. Modern chips contain tens of billions of transistors in an area smaller than a fingernail.

The gate dielectric - An ultra-thin insulating layer, just a few atoms thick, separating the transistor gate from the channel it controls. This layer must be essentially defect-free to function correctly.

The contact layer - Tiny vertical pillars of conducting material that connect the transistors to the first metal wiring layer above. These contacts must be precisely aligned with the structures below.

Metal interconnect layers - Multiple layers of copper wiring, each separated by insulating dielectric material, that connect transistors across the chip and carry power from the edges inward.

The passivation layer - A protective coating on the topmost surface of the chip, shielding it from moisture, dust, and physical damage.

Bond pads - Exposed metal areas on the chip surface where electrical connections to the package will be made.

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## Testing and Yield

### Why Testing Matters

A chip that leaves a foundry without testing is a liability, not a product. In automotive, medical, or data center applications, a failed chip can have consequences far beyond an inconvenient malfunction. Testing is the quality gate that stands between manufacturing and the real world.

### Yield

Yield is the percentage of chips on a wafer that pass all quality tests and function correctly. It is the central economic metric of chip manufacturing.

A new process node typically starts with low yield when first introduced. Foundries invest intensively in process optimization to improve yield over time. Even small yield improvements have enormous financial impact: on a wafer containing 500 dies, moving from 80% to 85% yield produces 25 additional functional chips per wafer at essentially no marginal cost.

This is why foundries guard their process knowledge so carefully - yield improvement is a competitive advantage worth billions of dollars per year.

### Wafer Probe Testing

Before a wafer is diced into individual dies, automated probes contact each die and run electrical tests to verify basic functionality. Dies that fail are identified and discarded before packaging, avoiding the cost of processing a chip that is already known to be defective.

### Defect and Contamination Control

At the nanoscale, even microscopic contamination is catastrophic. Foundry cleanrooms maintain air purity thousands of times greater than a hospital operating theater. Engineers wear full-body suits that prevent human hair, skin cells, and breath from entering the manufacturing environment. Airborne particle counts are monitored continuously.

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## The Global Supply Chain

The semiconductor supply chain is one of the most geographically distributed industrial systems ever built. No single country makes chips from start to finish.

| Stage | Key Geography |

|---|---|

| Silicon wafer production | Japan, Germany |

| Lithography and fab equipment | Netherlands, USA, Japan |

| Chip design (Architects) | USA, UK, Europe |

| Advanced chip fabrication (Foundries) | Taiwan, South Korea |

| Chip packaging and testing | Taiwan, South Korea, Malaysia, Philippines, Vietnam |

| End product manufacturing | China, South Korea, USA, Europe |

This distribution reflects decades of specialization. Taiwan built TSMC into the world's most advanced foundry through sustained government investment, deep engineering talent, and accumulated manufacturing expertise. Japan dominates silicon wafers and specialty materials - industries that grew alongside Japan's electronics boom in the 1970s and 1980s. The Netherlands became home to ASML through excellence in academic research and precision engineering.

### Supply Chain Fragility

The 2021 global chip shortage exposed the fragility of this system. COVID-19 caused factory shutdowns across multiple stages simultaneously. Demand for consumer electronics surged while manufacturing capacity was constrained. Logistics disruptions added weeks to shipping times. Automotive companies - holding too little chip inventory - saw production lines halt for months.

The lesson: a supply chain optimized for efficiency is not the same as one built for resilience. When disruption hits any node in a tightly integrated global system, the effects travel fast.

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## Economic Drivers

### The Cost of a Leading-Edge Fab

Building a semiconductor fab capable of producing chips at the leading edge - 3nm or 2nm - costs between $15 billion and $20 billion, a figure that rises with each new technology generation. Equipment must be continuously refreshed as processes advance. Fabs operate 24 hours a day, seven days a week, because the fixed cost of a fab runs whether or not it is producing chips.

### Economies of Scale

Chip manufacturing benefits from scale at every level. A larger fab spreads fixed costs over more wafers. A foundry serving many customers runs its equipment more continuously. Larger volumes allow better negotiation on equipment and materials. This is why only a handful of companies can afford to operate at the leading edge - the capital requirements are so large that only companies with significant scale and revenue can sustain the investment cycle.

### The Role of Foundry Pricing

Foundries charge customers per wafer - a price that reflects the process node, the complexity of the manufacturing steps involved, and the foundry's capacity utilization. As a process node matures and yield improves, the cost per functional die falls, which reduces the cost of chips manufactured on that node and enables new applications and price points.

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## Geopolitical Bottlenecks

### Taiwan's Strategic Position

Taiwan produces roughly 60% of the world's semiconductors and over 90% of the most advanced chips - those manufactured at 7nm and below. TSMC alone accounts for more than half of global foundry revenue.

The implications are significant. A disruption to Taiwan's chip production - from a natural disaster, a political crisis, or a conflict - would affect nearly every industry that depends on advanced chips worldwide. This concentration gives Taiwan enormous leverage in global technology and geopolitics, and makes it a focal point of strategic concern for governments across every major economy.

### Export Controls and Technology Restrictions

Governments use export controls to restrict the flow of sensitive semiconductor technology to foreign parties. In recent years, these controls have become one of the most consequential tools of technology policy:

- The United States has restricted exports of EUV lithography machines and advanced chip manufacturing equipment to China, citing concerns that the technology could be used for military purposes.

- The Netherlands has imposed its own export restrictions on EUV machines following coordination with the US.

- Japan has enacted controls on certain semiconductor manufacturing equipment and specialty chemicals.

These restrictions have significantly slowed China's ability to develop leading-edge domestic chip manufacturing - and have made access to Toolmaker equipment a major geopolitical flashpoint.

### The Race to Build Domestic Capacity

Governments have launched major programs to build semiconductor manufacturing capacity at home:

- The US CHIPS Act (2022) - $52 billion in federal subsidies to support domestic chip manufacturing and research.

- The EU Chips Act (2023) - €43 billion in public and private investment aimed at doubling Europe's share of global chip production by 2030.

- Japan's domestic strategy - Billions in state support to attract TSMC and rebuild domestic advanced manufacturing capability.

- China's domestic program - Hundreds of billions in state investment aimed at building an independent semiconductor supply chain.

These programs reflect a fundamental shift: semiconductors are no longer treated as a commercial product alone. They are now treated as critical national infrastructure.

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## Lesson Milestone Checklist

Work through this checklist before moving to the next lesson. Each item corresponds to something covered in this page.

- [ ] I can explain what a foundry is and how it differs from a chip designer

- [ ] I can describe the pure-play foundry model and why chip companies trust foundries with their designs

- [ ] I can explain how silicon wafers are made and why starting material quality affects yield

- [ ] I can describe what lithography is and explain the basic steps in the process

- [ ] I can explain what EUV lithography is, why it exists, and why ASML is the only manufacturer

- [ ] I can describe the difference between FEOL and BEOL fabrication

- [ ] I can name at least four FEOL manufacturing steps and describe what each one does

- [ ] I can explain what ion implantation is and why it is used

- [ ] I can explain what BEOL metallization is and why multiple metal layers are needed

- [ ] I can explain what yield means and why small yield improvements have a large economic impact

- [ ] I can identify which countries dominate each major stage of the global semiconductor supply chain

- [ ] I can describe what caused the 2021 chip shortage and why it spread across so many industries

- [ ] I can explain why a leading-edge fab costs $15–$20 billion and why so few exist

- [ ] I can describe Taiwan's role in global chip production and why it is a geopolitical concern

- [ ] I can name at least two government programs launched to build domestic chip manufacturing capacity

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## Key Terms

| Term | Definition |

|---|---|

| Fab | A semiconductor fabrication plant - the factory where chips are manufactured |

| Pure-play foundry | A foundry that manufactures exclusively for others and does not design or sell its own chips |

| Silicon wafer | A thin circular disk of ultra-pure silicon used as the base for chip manufacturing |

| Ingot | A large cylinder of pure silicon crystal, grown through a controlled process and sliced into wafers |

| Lithography | The process of using light to project circuit patterns onto a wafer coated with photoresist |

| Photoresist | A light-sensitive chemical applied to a wafer before lithography; changes chemically when exposed to light |

| Photomask | A glass plate etched with a circuit pattern, used to project that pattern during lithography |

| EUV | Extreme Ultraviolet - advanced lithography using 13.5nm wavelength light, enabling the smallest circuit features |

| DUV | Deep Ultraviolet - an older lithography technology, capable of defining features to approximately 7nm |

| FEOL | Front End of Line - the phase of manufacturing where transistors are formed in the silicon |

| BEOL | Back End of Line - the phase where metal wiring layers are added to connect transistors |

| CVD | Chemical Vapor Deposition - a process for depositing thin material layers onto a wafer |

| ALD | Atomic Layer Deposition - an extremely precise deposition technique, adding one atomic layer at a time |

| Ion implantation | Firing charged particles into silicon to alter its electrical properties in specific regions |

| Doping | Introducing impurities into silicon to make it conductive in controlled ways |

| Annealing | Heating a wafer after ion implantation to activate implanted atoms and repair crystal damage |

| Yield | The percentage of chips on a wafer that pass quality testing and function correctly |

| Process node | A generation of manufacturing technology, named for the minimum transistor feature size (e.g., 3nm, 5nm) |

| Gate dielectric | An ultra-thin insulating layer separating the transistor gate from its channel |

| Interlayer dielectric | Insulating material placed between metal wiring layers in BEOL |

| Passivation | A protective coating applied to the topmost surface of the chip to shield it from damage |

| Export controls | Government regulations restricting the export of specific technologies or equipment |

| CHIPS Act | US legislation (2022) providing $52 billion in subsidies for domestic semiconductor manufacturing and R&D |

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## Companies to Know

| Company | Country | Role |

|---|---|---|

| TSMC | Taiwan | World's largest and most advanced pure-play foundry |

| Samsung Foundry | South Korea | Second-largest foundry; competes at the leading edge |

| GlobalFoundries | USA | Major foundry for mature and specialized process nodes |

| UMC | Taiwan | Significant mid-tier foundry |

| SMIC | China | China's largest domestic foundry |

| ASML | Netherlands | Sole manufacturer of EUV lithography machines |

| Shin-Etsu Chemical | Japan | World's largest silicon wafer supplier |

| Sumco | Japan | Major silicon wafer manufacturer |

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## What to Study Next

🔧 Toolmakers - Explore the companies that supply foundries with everything they need to operate: lithography machines, etching tools, deposition equipment, and specialty chemicals. Understanding Toolmakers shows you why foundry capability depends on just a handful of equipment companies.

🏛️ Architects - Learn how chip designers create the design files that foundries manufacture. Understanding Architects shows you what goes into a chip before it ever reaches a fab.

⚙️ Workhorses - Discover what happens after a foundry finishes a wafer: how chips are tested, packaged, and assembled into the products you use every day. Workhorses are where the chip's journey from silicon to device is completed.

The Four Pillars - How They Connect - See the full semiconductor supply chain as a connected system, and understand how a decision made at any one pillar ripples through all the others.

Explore in SemiTrack - Take what you've learned into SemiTrack, KvantaCore's semiconductor research platform. Search for any foundry from this lesson, trace their supply chain connections, compare process nodes across manufacturers, and follow the latest developments in chip manufacturing and geopolitics.

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